Integrated circuit I/O interface is widely used for transmission of signals between chips. An I/O interface can be realized by a digital signal receiver, and the simplest digital signal receiver can include a pair of inverters 102 and 104 connected in series, as shown in FIG. 1. Further, as shown in FIG. 2, the inverters 102 and 104 in FIG. 1 can be CMOS inverters, each comprising a pair of NMOS and PMOS devices connected in series between a power supply voltage and a ground. When the input signal IN is a high logic level (“high”), the NMOS device in the inverter 102 is turned on, such that the output OUT1 of the inverter 102 is a low logic level (“low”), then the PMOS device in the inverter 104 is turned on, such that the output OUT of the inverter 104 is high. Similarly, when the input signal IN is low, the PMOS device in the inverter 102 is turned on, such that the output OUT1 of the inverter 102 is high, then the NMOS device in the inverter 104 is turned on, such that the output OUT of the inverter 104 is low.
When the amplitude of the input voltage is rail to rail (meaning the input voltage of the device can go as high as the power supply voltage and as low as the ground), the gain of the PMOS device is the same as that of the NMOS device, making the output slew rate of the inverter substantially balanced.
However, when the amplitude of the input voltage is not rail to rail (e.g., small input signal having a voltage swing within the power and ground), one of these two PMOS and NMOS devices works under a smaller overdrive voltage than the other, such that the output of the inverter is associated with the stronger one of the PMOS and NMOS devices. In other words, the signal swing at the inverter output is rather asymmetrical and does not have balanced rise and fall times. In this case, the higher the frequency of the input signal is, the poorer the speed performance of the digital signal receiver is.
Therefore, there is a need to provide a receiver circuit that has high gain and improved speed performance.